MSTSCLHIGH=2_CLOCKS, MSTSCLLOW=2_CLOCKS
Master timing configuration.
| MSTSCLLOW | Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW. 0 (2_CLOCKS): 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 1 (3_CLOCKS): 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 2 (4_CLOCKS): 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 3 (5_CLOCKS): 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 4 (6_CLOCKS): 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 5 (7_CLOCKS): 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 6 (8_CLOCKS): 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 7 (9_CLOCKS): 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. |
| RESERVED | Reserved. |
| MSTSCLHIGH | Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 0 (2_CLOCKS): 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 1 (3_CLOCKS): 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 2 (4_CLOCKS): 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 3 (5_CLOCKS): 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 4 (6_CLOCKS): 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 5 (7_CLOCKS): 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 6 (8_CLOCKS): 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 7 (9_CLOCKS): 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |